Research On FPGA Design Of Low Spurious DDS

Direct digital frequency synthesis(DDS)technology is a new generation of frequency synthesis technology.Because it has the advantages of high frequency resolution,fast frequency switching,and continuous phase change,it is widely used in radar and communications.The all-digital structure of the DDS also makes it have the disadvantages of large spurious and narrow output bandwidth.A large number of studies on DDS have directly or indirectly reduced the spuriousness of DDS to improve spectral purity.With the continuous development of technology,higher and higher requirements are also put forward for the spectral purity,operating frequency,and power consumption of direct digital frequency synthesizers.This dissertation focuses on reducing the spurious of DDS.Based on the analysis of DDS structure,phase truncation error and amplitude quantization error,several spurious DDS structures are studied and analyzed.A scheme combining ROM compression and Taylor series principle is proposed.The spectrum of the designed DDS is analyzed by Matlab to verify its spurious reduction effect.The main research work of this paper is as follows:1.Introduces the working principle and basic structure of DDS and the functions of each major component.It analyzes the phase truncation error and amplitude quantization error of DDS in detail,and analyzes the spurious spectrum of DDS under different conditions through Matlab simulation.2.Study the phase-to-amplitude converter.Some traditional ways to reduce spurs are introduced,and then the three phase-conversion schemes of the polynomial interpolation algorithm,the structure without phase truncation error,and the Cardarilli structure are analyzed.Because the Cardarilli structure has a high spurious-free dynamic range(SFDR)and higher ROM compression ratios were studied in depth and then the lookup tables were further optimized.The Taylor series interpolation algorithm is studied and the phase amplitude conversion result is modified according to the Taylor series formula to reduce the error.Matlab simulation results show that the proposed DDS scheme can achieve high SFDR.3,DDS FPGA implementation and verification.The proposed DDS design scheme is implemented on an FPGA.The phase accumulator has a 32-bit word length and an output amplitude of 18 bits.Each module was designed and verified by simulation.Through the pipeline technology to optimize the design of the DDS,to increase the maximum operating frequency,the maximum operating frequency in Stratix II can reach 310 MHz.And use ModelSim to simulate the DDS.The result of spectrum analysis shows that SFDR can reach 133 dB.