Design And Analysis Of On-Chip ESD Protection Devices For CMOS IC

Electrostatic discharge (ESD) causes a significant percentage of the failures in the electronics industry. The shrinking size of semiconductor circuits, thinner gate oxides, complex chips with multiple power supplies and mixed-signal blocks, larger chip capacitance and faster circuit operation, all contribute to increased ESD sensitivity of advanced semiconductor devices. Therefore, understanding and controlling ESD is indispensable for higher quality and reliability of the state-of-art device technologies.This thesis addresses on-chip ESD protection for CMOS technology. Various ESD protection device structures are designed in different deep sub-micron processes, by testing and analyzing their ESD performances, the main work and conclusion are listing as follows:1) The characteristics of FOD (Field Oxide Devices) based ESD protection devices for input, output and power rails were inverstigated, three main FOD devices were fabricated in HHNEC 0.18-μm STI EEPROM CMOS technology. By using TLP tester, the effects of the feature size dependent FOD's ESD characteristics and its design rule were analyzed. A floating square poly island FOD was proposed, which showed a simple structure and good ESD protection ability.2) By using ISE-TCAD transient simulation and TLP test technique, NMOSFET ESD protecttion structures under different gate bias fabricated in a 0.35-μm CMOS process with various active widthes and channel lengthes were researched. It pointed out that gate bias would degrade the second breakdown current (It2) of the NMOSFET ESD protection devices, its relative gate biased MOSFET ESD test and design methodology were proposed and summarized, respectively.3) A novel square layout design of SCR device was designed which ensured uniform current distribution and better robustness.4) A new dual direction silicon contolled rectify (DDSCR) decice was designed. In HJTK 0.18-μm LOGIC and MIXED_MODE RF CMOS technologies, PMOS and NMOS were successfully embedded into the DDSCR to acheive low voltage triggering mechanism, respectively. The low voltage triggering DDSCRs feature a symmetric TLP I-V characteristic, it is very area efficient and suitable for mixed mode IC or RFIC. Layout and metal routing play an important role in DDSCR ESD design, and its relative techniques were investigated and parasitic lateral BJT effect was found in layout of square DDSCR devices. Modified ESD protection device structruces were proposed after the realized devices, and the device characteristics were simulated by ISE-TCAD.