The Design Of QPSK Modulator And Demodulator Based On FPGA

QPSK modulation is widely used in the modern communication since it has many advantages, such as its high spectrum efficiency, low SNR requirement compared with other modulations at the same BER, and comparatively simple circuit structure. FPGA (Field Programmable Gate Array) has many features such as powerful function, small investment and short period in development process, repeatedly programmable changes, confidentiality performance and intelligent development tools. Using FPGA in modulator and demodulator, not only reduces the cost of products and the volume of equipment and meets the needs of the system, but also has greater flexibility and controllability compared with ASIC. The task is to design the data rate 1 Mb/s, carrier frequency 10 MHz QPSK modulator and demodulator based on FPGA.The basic theory of QPSK system is researched in this paper, including the basic principles of modulator and demodulator, and the design diagrams are given. The realization methods of both numerically controlled oscillator (NCO) and the shaping filter are introduced in modulator. The theory of Costas Loop commonly used in the QPSK demodulator and bit synchronization Digital Phase Locked Loop (DPLL) is analyzed in demodulator. Based on introducing the principle and tracing performance of PLL, the emphasis is the derivation of PLL noise performance. On this basis, QPSK modulator and demodulator are designed using HDL (hardware description language) in Altera QuartusⅡsoftware. The design of NCO, shaping filter, Loop Filter and bit synchronization is illuminated in detail. NCO and shaping filter are implemented by using look-up table method. Loop Filter is realized by IIR filter. And the DPLL is used in the Bit Synchronization.The software design of every module is introduced in detail based on FPGA. The result if realization shows that the design in the paper is right. So the design owns some theoretical and practical significance.