Digital 2DPSK/QPSK If Demodulator Design And Implementation

In the field of digital communications,multi-band digital phase modulation(Multiple Phase Shift Keying,MPSK)is a very important digital modulation technology,widely used in satellite and civilian communications equipment.And one of binary phase shift keying(Binary Phase Shift Keying,BPSK)and quadrature phase shift keying(Quadrature Phase Shift Keying,QPSK)technology is relatively mature,relatively broad,and because when BPSK modulation demodulation prone phase inversion,so engineering applications more differential phase shift keying(Differential Phase Shift Keying,DPSK)modulation.Therefore,an object recognition DPSK and QPSK modulation formats to seem even more important.When the signal format is identified by the signal processing multiple phase difference,the result obtained by the processing for encoding the identification code has been designed according to the rules,the coding statistics obtained for the final use of both DPSK and QPSK signal recognition.The recognition rate of the algorithm is completed by simulation software tests to verify the performance of the recognition algorithm using FPGA design software to complete the functional simulation.Demodulator for demodulating the principle aspects of the text DPSK/QPSK baseband digital demodulation platform for analysis and simulation.mainly include:The principle of lock-in technique and performance analysis.And for the feedback judgment carrier used in the system of the synchronous demodulation ring design,the important parameters calculated by the MATLAB simulation synchronizer ring.Synchronization of the working principle and implementation method bits for analysis.Lead-lag focusing ring FPGA design implementation and Xilinx's ISE14.2 build environment for a detailed functional simulation and timing simulation.Demodulation system through the results using the signal recognition as a modulation mode select port.After completion of DPSK or QPSK signal encoding conversion output data,complete the data demodulation.Final on FPGA platform for the realization of the demodulated signal recognition algorithm for authentication.Use ISE14.2 VHDL development environment for system programming and timing simulation to verify its function and timing is correct.