| To fully exploit instruction level parallelism and improve Instruction per Cycle, nowadays high-powered superscalar processors have large issue widths. However, as a processor's issue width is enlarged, hardware complexities of critical components in the pipeline like physical register file, instruction issue logic and bypass logic increase rapidly, which causes the wire lengths and delays greater. Especially as the feature sizes are getting smaller, wire delays limit the rise of the processor performances. On the other hand, power and area scale quadratically with the issue width rises. Obviously, simply increasing the issue width of the superscalar with a traditional architecture costs too much. Through clustering these critical components, each of which only needs to support a small issue width, the delay, power and area problems are alleviated. For the total issue width of the pipeline is comprised those of all the clusters, it is not decreased.In the thesis we designed a 64-bit 11-stage clustered superscalar processor. We devised a high-performance front end including combining branch prediction and rename techniques. Branch predictor with high veracity is able to mitigate the impact of branch misprediction to pipeline performance, and rename technique helps remove the false dependence between instructions, which can deeply exploits the instruction level parallelism. Besides, a clustered back end was designed. Several factors were considered in cluster design: Two homogenous clusters were employed to reduce the complexity of instruction dispatch logic. Each cluster was composed of instruction issue logic, physical register file, bypass logic and 4 function units. To balance the workload between clusters, a modulo-3 instruction dispatch scheme was designed. Execution results were broadcasted to the other cluster through the cross bar to communicate between clusters. At last, we built a simulation platform and verified the basic functions of the designed processor. |
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