Design Of Foint-Point FFT Processor IP

With the rapid development of electronic and integrated circuit technology, digital signal processing has been widely applied in various domains, like speeching and graphing processing, communication, multimedia.FFT plays an important part in digital signal processing as a basic calculation. However, when N is a little great,the calculation quantity of radix 2 FFT algorithm is large.As N is a little great,it is very necessary of using great algorithm of reducing the calculation quantity and reducing difficult of design.It is strongly theory and real signification to research on the FFT algorithm and its method for design.Along with the application of FFT processor more and more extensive,designs FFT processor IP,has very meaningful. Designing FFT of IP core, the FPGA chip production manufacturer is in the leading position, but the price is expensive, as,it is very difficultly of widely apply in each domain.Therefore , independently develops FFT the IP core, cuts its price, by obtains the widespread application in various domains.This paper studies the implementation of FFT IP core.It includes selection and validation of the arithmetic,design of whole architecture and modules,implem-entation and simulation of the system.This design adopts the algorithm of Cooler-Tukey ,and use of that form of float to improve computing accuracy of FFT processor.In order to improve operational speed,the pipeline technology is introduced in the floating-point adder and multiplier.In this paper, it realizes a floating point FFT system of 256-point by using hardware description language at the interface of QuartusII 6.0 and Modelsim 6.1.Then it finishes simulation and synthesis of the system on Cyclone II EP2C35F484C8.The simulation indicates that the result of calculation can reach equivalent precision and the operation speed of FFT can satisfy the request of commonly real-time signal processing.