Sense Amplifier Design In Deep Sub-Micron Technology

Sense Amplifier is nowadays widely used in the memory system design, IO design to improve speed. This thesis is focused on SRAM sense amplifier in deep sub-micron design.The tradeoff among area, speed, power consumption and yield is the most important design issue of the sense amplifier. With the process scaling down to deep sub-micron,characteristics of devices are not so stable which may cause mismatch of the symmetrical devices. The differential small signal may be amplified to the wrong direction. To increase devices size is not a reasonable method when considering the tradeoff among area, speed, and power consumption when keeping a sound yield. This issue becomes the most important design difficulty in deep sub-micron technology. Monte Carlo analysis is used in device analysis and circuit design to evaluate the mismatch effect.This thesis first analyzes basic design of sense amplifier in deep sub-micron system, compares and discusses the mismatch problem, and then the new design is presented. The sense amplifier circuit is commonly symmetrical which needs a matched layout design, so the system design and layout design is also discussed at the end.