Organization Design Of Broadband Satellite Gateway Processor

With the rapid development of satellite communication technology and Internet, in recent years, people have shown great interest in carrying IP traffic over the satellite channel and integrating satellite network with terrestrial IP networks. To provide high throughput transmission channels for IP traffic with good QoS guarantee, the onboard gateway processor has became one of the hot spots in the research field of broadband satellite. And a good architecture of the gateway processor becomes a crucial issue for the whole satellite network system.This thesis begins with a description of the onboard processing technology. In consideration of the processing speed and QoS guarantee, this thesis comprehensively analyzed two possible approach of switching. A switching method based onMPEG2-TS at layer 2 was selected, and then possible ways of carrying IP traffic in MPEG2-TS were mentioned. After looking into the design of commercial network processor, this thesis summarized the design trend of NP using in backbone network through classifying different NP application. Combining the properties of the second layer switching, an architecture-level solution was proposed. By separating the segment-reorganization and TX queue functions from the PE and limiting PE accessing DRAM, PE could focus on analyzing and processing packets. Through avoid the conflict of accessing memory, the average idle time of PE was reduced and utilization of PE was improved, thereby the system throughput was increased. Finally using NePSim2 simulating two groups of test program running in different number of PEs, this thesis evaluated performance of the new architecture and verified the feasibility of the proposed solution.