Power/Ground Planes Analysis And Optimization In Package And PCB

PI has become a limiting factor for the overall performance of modern chip design due to the current surges caused by SSN. As an indispensable part of the power delivery system, the power/ground (P/G) planes provide coupling paths for the large current flows. And a robust P/G plane design is crucial to meeting performance targets and guaranteeing reliable operations. To ensure the robustness of the design, it is essential to have the exact analysis of the noise on the P/G plane pairs and the optimization of P/G planes to mitigate the noise. Adding in-package decoupling capacitors is one of the most efficient ways to improve the in-package power integrity.In high performance microprocessors, the package may have many vias, decoupling capacitors, irregular geometries and multiple plane layers. The complex structure and various border effects restrict the size of the segment in regular partitioning when discretizing the P/G planes. A small enough segment would guarantee the accuracy at the cost of memory and CPU time. In this paper, we propose an irregular partitioning strategy in which the P/G planes can be partitioned into different rectangular shapes according to the vias, decoupling capacitors or other details of the structures. Such a strategy is more practical and efficient, because larger segment can be used for non-critical regions and smaller for regions full of vias or decoupling capacitors. We integrate this strategy into TMM to analyze the multiple-layer P/G planes with complex structures. Based on the improved TMM method, we have proposed a methodology for in-package decoupling capacitor optimization on multiple-layer P/G plane. Compared with previous work, our method can gain more accurate results with less CPU runtime. The main contributions of this paper are summarized as follows.(1)We propose an irregular partitioning strategy to divide the P/G planes. This strategy partitions the planes with different-sized segments depending on the specific structures or requirements.(2)We apply the irregular partitioning strategy to TMM method. Based on that, we simplify the computation procedure of TMM and give a fast flow for multiple-layer P/G planes analysis.(3)We use the improved TMM for fast decoupling capacitance allocation. A methodology to guide the decap optimization is also proposed. When decoupling capacitors are added or deleted, we use a matrix refinement technique to speed up the transmission matrix update. Experimental results show that our methodology can optimize the target impedance very efficiently and accurately.