System Level Supply Noise Analysis And Management

Low power system-on-chips(SoCs)are now at the heart of Internet-of-Things(IoT)devices,which are well known for their bursty workloads and limited energy storage-usually in the form of tiny batteries.To ensure battery lifetime,DVFS has become an essential technique in such SoC chips.With continuously decreasing supply level,noise margins in these devices are already being squeezed.During DVFS transition,large current that accompanies the clock speed transition runs into or out of clock networks in a few clock cycles,induces large Ldi/dt noise,thereby stressing the power delivery system(PDS).Traditionally,these supply noises in high performance SoCs are handled efficiently by improving routing and increasing the amount of on-chip decoupling capacitors.However,for mobile devices,implementation of these methods is increasingly challenging due to the limitation of area resources.Thus,this paper firstly analyses the efficiency of on-chip decoupling capacitor on supply noise reduction and the cost of on-chip area,several algorithms of decap placement and system model of power delivery system is employed in order to conduct experiment.Based on the model,further optimization possibility is explored.Due to the limited area and cost target,adding additional decap to mitigate such noise is usually challenging.Another common approach is to gradually introduce/remove the additional clock cycles to increase or reduce the clock frequency in steps,a.k.a.,clock skipping.However,such a technique may increase DVFS transition time,and still cannot guarantee minimal noise.In this work,we propose a new noise-aware DVFS sequence optimization technique by formulating a mixed 0/1 programming to resolve the problems of clock skipping sequence optimization.Moreover,the method is also extended to schedule extensive wake-up activities on different clock domains for the same purpose.The results show that we are able to achieve minimal-noise sequence within desired transition time with 53%noise reduction and save more than 15-17%power compared with the traditional approach.Moreover,the proposed method can not only optimize the sequence within the given timing constraint,but also provides opportunity to achieve power saving.At last,we further analyses the requirement reduction of on-chip decoupling capacitor achieved by proposed noise-aware transition sequence scheduling,which demonstrate that the proposed method also provides the capability to explore design cost.