The FPGA Implement Of Multi-Dimensional Concatenated Single Parity Check Codes

Since Shannon proposed and proved famous coding theorem in 1948, people have been making great efforts to look for a kind of good code, whose performance could approach to the Shannon's theoretical limit. In 1993, the emergence of Turbo Code brought the hope for thoroughly solve this problem. Initially, Turbo Code is a kind of parallel concatenated convolutional codes, although it have mature development of theoretical and practical applications, there are still some shortcomings of its own, such as low coding rate and high complexity of decoding, which make Turbo code has a certain limitations on development. At present the concept of Turbo Code have a great expansion, its son code is not only the convolutional code, but also block code; the form of concatenated can not only parallel but also series, and even the two mixed. The concatenated code composed with multi-son codes is named as multi-dimensional concatenated code.The parallel concatenated block code has been shown to yield remarkable performance close to theoretical limits, yet admitting a relatively simple iterative decoding technique. The Multiple Concatenated Parity Check-Code studied in this paper is this type of code, which has strong error-correcting ability. It takes the very simple Parity check code as son code to construct Multi-Dimensional Concatenated Code. In addition to simple encoding and decoding, Multiple Concatenated Parity-Check Code also has many advantages: high coding rate, relatively low encoding, decoding complexity, flexible variable length of the input data, and code rate etc. These advantages which the original Turbo codes do not have, are especially meaning to the theoretical study and practical application.This paper mainly presents three parts: The first part introduces Turbo Codes and Concatenated Block Coding Technology,expatiate the MAP (maximum a posteriori probability) decoding methods and iterative decoding thought; the second part studies encoding and decoding methods of the Multiple Concatenated Parity-Check code, deeply discussed and analyzed two different code-decode structure and MAP , Max-Log-MAP iterative decoding algorithm respectively; The third part focuses on the implement of Multiple Concatenated Parity-Check codes on FPGA. On the basis of theory studied in the former two parts, proposed the scheme for the 4-PC-SPC (4-Dimensional Parallel Concatenated Parity-Check) Code which is suitable for the implementation on FPGA, complete the encoder and decoder's implement on FPGA and made the corresponding test on the program proposed before. The encoder and decoder is optimized for high-speed modern communications technology, particularly in the higher hardware resources environment.