The Design And Implementation Of High-speed FFT In DTTB Modulating Transmitter

Nowadays, technology changes day by day. The fast development of the world's communication and information technology will bring the whole television broadcasting industry a noticeable evolution, of which the digital television should be a key point. The terrestrial digital television broadcasting system is one of significant parts in the broadcasting television system. At present, there are three digital television terrestrial transmitting standards: ATSC of USA, DVB-T of Europe, ISDB-T of Japan. To avoid the bulwark of intelligent property, the digital terrestrial television broadcasting transmitting standard, which ownes the intelligent property, is released in our country, and abbreviated DTTB.DTTB contains the multi-carrier modulation and the single-carrier modulation, only the multi-carrier modulation is discussed in this paper. OFDM is one multi-carrier modulation, OFDM may avoid high-speed equalization, and could confront impulse noise and propagation fading, and more importantly, it improves the efficiency of frequency spectrum. OFDM can be implemented in DFT, but the direct calculation of DFT will taking a lot of operation. To deal with this, researtching the fast way to calculate DFT is important to the OFDM system and the performance of the whole system.The OFDM of DTTB system contains 3780 sub-carriers. Thereby, the FFT in this paper is 3780-point FFT, which mainly consists of two parts: the algorithm design and the logic implementation. As we know, 3780 is neither the power of 2 nor the power of 4, so the normal algorithm can't be used. This paper makes use of the hybrid radix, PFT and WFTA, etc to implement 3780-point DFT, which decreases the complexity and the gate number. Following measures are taken in this logic design: 1) mostly sharing the resource, for instance, adders and registers in TDM. 2) increasing the number of the pipeline, which can avoids the long path and deceases delay to increase working frequency. It is implied that the FFT in the area and speed meets our expectancy through the simulation and verification---the inner clock speed is over 90Mhz.