Design And Realization Of Digital Module In All-digital Shortwave Receiver

With the rapid development of communication technology, wireless communication becomes more and more integrated and individualized. Its communication velocity becomes higher and higher. There are several communication standards in current communication system. It is difficult to make these standards be compatible. As a good solution to this problem, Software Radio (SR) has become the focus of research. Software Radio (SR) makes the communication system break away from application-oriented design method. Therefore SR has been recognized as the next major leap forward in wireless communication.All-digital Receiver is a new architecture of wireless communication. As it makes the most of the RF's front end, the digital signal processing part can make the A/D sampling directly from the analog signals which received by the antenna and change them into digital signals. All-digital Receiver dispenses with many analog apparatus of traditional receiver and becomes an important development orientation of modern communication technology with its advantages of high capacity, small volume, low cost and excellent flexibility. The digital signal processing of the all-digital receiver can be implemented by DSP or FPGA/CPLD. Because these programmable logic devices have advanced real-time processing capability and make the system design more flexible, they are often be used in the digital receivers.In order to conquer the disadvantages of low capacity and compatibility in modem shortwave analog receiver, this paper makes designs for the digital module of all-digital shortwave receiver and achieves the hardware implementation by using FPGA. The main content of the paper includes:1. Research on all-digital shortwave reception scheme. This paper makes a comparison among several reception systems, analyzes their advantages and disadvantages and puts forward a reception scheme of this paper.2. Research on digital down conversion (DDC), multisampling technology and coding/decoding technology upon the communication channel. Taking the hardware structure of the FPGA into consideration, this paper designs a pipelining DDC, a multilevel CIC filter, a 4FTSK demodulation and a viterbi encoder of long constraint length.3. By using common algorithms in DSP and advanced simulation tools such as matlab,Modelsim and taking the characteristics of FPGA into consideration, this paper simulates the digital circuitry of the system and implements the system with smaller magnitude of hardware and quicker speed.