Research And Development Of A DVB-T Receiver Chip

An improvement resolution of present DVB-T specification is put forward. a system resolution of DVB-T digital receiver is designed and implemented using FPGA and some proposals is presented based on these theories and some improved algorithm resolutions and implements some modules and algorithms using HDL. Then the functions of DVB-T receiver is verified and the logic circuits are synthesized. Several aims have been achieved in this project: 1, LUT method and iteration method are used to implement the BCH(67,53) decoder. The advantage and shortage of these two methods are compared. The two methods are improved respectively. The improved LUT method reduces the capability of the look-up table by 97.2%, and improved iterative method makes the hardware architecture simple and the computation speed increases obviously. 2, RS(204,188) decoder is implemented using an serial inverse free iterative algorithm. This algorithm avoids multiple inversion in Galois Field and simplifies the architecture. 3, A base band converter is designed. The IF sampling frequency is computed. Two hardware implementations of scattered trigonometric function are introduced. One is Cordic algorithm base on real time computation, another is LUT method. The LUT method is applied to NCO implementation. The NCO used in base band converter is improved. After improving, the look-up table capability of NCO is reduced by 75%. 4, Efficient multiple inversion algorithm in Galois Field is quoted. And it saves the gates resources 87% compared with Fermat algorithm. 5, Some other modules such as bit deinterleaver, frame alignment are implemented according to the DVB-T specification. 6, Multi-layer system verification model based on reused module is introduced. Single module verification model is introduced and the RS module is regarded as an example.