Design Of JTIDS Base Band Data Processing Module Based On FPGA

United States Department of Defense chooses Linkl6 as its high-speed visual range tactical data link. Linkl6 is composed of time division multiplex (TDMA) protocol, Joint Tactical Information Distribution System (JTIDS) and TADIL J information standard, jamming techniques, such as direct sequence spread spectrum (DSSS), frequency hopping (FH) and so on, are adopted in it. Link16, and Linkl6 has many characters as high-capacity, high-security, strong anti-interference ability, flexible, complete function, etc. Considering the important function in modern warfare, it is necessary to study Link16.JTIDS terminal is the communication carrier of Link16, what takes charge of the information processing before sending data and information reduction after receiving data. JTIDS base band data processing contains JTIDS transmission code generation and JTIDS message reduction, and sub modules as RS encoding, block interleaver, CCSK tamed spread spectrum, CCSK codes encryption and a series of adverse processing constitute the system. FPGA technique is adopted to design a breadboard that realizes JTIDS base band data processing, so as to satisfy the demand of JTIDS test in the laboratory.Firstly, tactical data link and Link16/JTIDS are introduced. According to the format specification of TADIL J information standard, technologies related in the process of data processing are expounded. Verilog HDL and QuartusⅡ6.0 software are used to design the software of sub modules, and the simulation results indicate the correctness of the design. By means of synchronizing and integrating the sub modules, transmission code generating system and message reduction system are designed, and schematic diagrams and simulation results are provided. OrCAD software and PADS software are adopted to design the hardware of the JTIDS base band data processing system. In the course of debugging the hardware, problems presented are analyzed and the solutions are provided. Finally, the advantages and shortages are indicated in the work summary and follow-up research is planed.The correction and reliability of the software and hardware are confirmed by means of the test. Because of the module's high integrated level, less resources employed, and preposing ports and postpositive ports are obligated, this module can be implanted in relevant system to finish the test of performance related, and can also add in JTIDS radio frequency(RF) module so as to be a completed JTIDS terminal.