Timing Recovery In COFDM System

The Digital TV system is a trend in the TV broadcasting. Comparing with theAnalog TV system, it has obvious advantages. DVB is developed as HDTV standardsby more than 170 organizations in Europe. It mainly comprises satellite (DVB-S),terrestrial (DVB-T) and cable (DVB-C) digital TV systems. DVB-T takes use ofCOFDM modulation model. Comparing with single carrier modulation model,COFDM has less ICI and has higher band efficiency. This paper is about algorithmsof timing recovery used in DVB-T channel receiver system and its implementation inFPGA (Field Programmable Gate Array)Firstly, the DVB-T standard and COFDM system is researched in this paper,especially the part which is used in timing recovery module. The infection of timingerror is discussed in the paper. After deeply analysing and comparing the detectingand recovery methods in theory, the proper algorithm is worked out.Secondly, the simulation is achieved with the help of Matlab. The software iswritten based on Matlab and is improved continually. With a view of hardware level,the inside of every module is properly arranged and the interface of every module isdefined in a convenient way. The source data of simulation is built to estimate theeffect of the timing recovery module. By simulating the system in various situations,we improve the module and develop the new arithmetic.Finally, the modules are transformed into RTL, and the control clock is addedinto these modules. The hardware language is Verilog HDL. After simulating withModelsim and synthesizing with Quartus, the hardware design based on FPGA isimplemented.The main contributions of this paper are proposing the algorithm and FPGAimplementation scheme of timing recovery applicable for DVB-T system.