Architecture Design And Bus Analysis For Source Decoding System Of Digital Television

With the development of IC design technology and the increasing of the circuit density, traditional ASIC design methodology can no longer satisfy the requirements of the design complexity and the time urgency to market. In the digital television area, the popularization of the digital television and the development of Set-Top Box technology also challenge the traditional ASIC based design. SoC design theory and technology make the system chip become more and more predominant in the IC design area. This thesis made some system analysis and design practice for the source decoding system of digital television based on the SoC design methodology.SoC design mainly focused on system design methodology, IP reuse methodology, etc. With system design methodology, we made requirement analysis according to the MPEG-2 standard and the current market status. Functional and performance definitions about the system were made according to the relative theory and the features of each sub functions of the system. What's more, this thesis proposed the BTV3000 architecture for the source decoding system.The BTV3000 has a dual-core architecture based on ARM microprocessors, a bus architecture based on AMBA2.0 AHB and a memory architecture based on DDR SDRAM. Qualitative and quantitative analysis to the BTV3000 architecture were made from the aspects of system performance requirements such as the rationality of the hardware and software partition, memory throughput, bus bandwidth, etc.As to the IP-reused technology, we took the design of video decoding core as an example. Video decoding is the most importance functional core and the most critical part of the system since its bandwidth consuming and computation complexity. Functional implementation is the key for the core design, but system resources and performance requirements should also be considered. Taking account of these factors, we mainly introduced the design of variable length decoding using the barrier shifter and the motion compensation using pipeline structure for the core design.Bus performance is an important factor to system design, especially for systems based on AHB bus. Bus utilization and bus contention between multiple masters affected the system performance most. The current BTV3000 adopts divided bus architecture of system bus and memory bus. The system bus used a single-layer AHB bus structure with delayed priority arbitration scheme, while the memory bus used the single-layer AHB bus structure but a simple priority arbitration scheme.Finally, we introduced Mentor's Seamless co-verification platform, and finished the function verification and the performance analysis for the BTV3000 system, mainly focused on the effect of the bus arbitration schemes to the bus performance.