Research On Inter-Frame-Prediction Technology In AVS Video Encoder And It's Hardware Implementation

Inter-prediction is a key technique in video compression standard with high compression ratio such as H.264,MPEG-4 and AVS. It takes use of the relativity of the neighboring video frames to compress video information. The difference between the neighboring frames is quite little for most video sequences, so we use this strong correlation to achieve much higher compression ratio than intra-prediction. As the compression ratio is increased by inter-prediction, the complexity also increases dramatically, which brings us difficulty to realize it on a chip.This paper mainly study on the hardware-oriented inter-prediction in AVS video coding standard. First, we propose a predicted center based small search range algorithm, which decreases the computation and memory cost dramatically. Secondly, we propose an algorithm which can implement half-pixel and quarter-pixel motion estimation in parallel. This stategy reduces the processing time and insures the real time coding. Then we propose a low-complexity algorithm to realize symmetric mode, which improves the coding performance greatly. Because there is no mature algorithm for RDO off, we have done research on the mode decision algorithm based on hardware realization and proposed a series of hardware-oriented mode decision strategy.By comparing multiple algorithms in inter-prediction, we make a tradeoff between coding performance and hardware cost. Finally we accept an algorithm system and propose its VLSI architectures. First, we propose area-oriented and power-oriented integer-pixel motion estimation architectures respectively. And then, for fractional-pixel motion estimation, we propose a VLSI architecture which can process the half-pixel and quarter-pixel motion estimation in parallel. Finally, we discuss the stategy to extend our design to HD requirement (1920xl080@60fps). Our Design has been synthesized and simulated in FPGA and Design Compiler. Compared to the reference of related VLSI design, our design has the advantage of lower complexity, smaller size and higher speed.We also explore the versatile architecture in our AVS encoder chip design. First, we design a versatile architexture to combine integer-pixel and fractional pixel motion estimation to improve the utilization of hardware. Secendly, we propose a versatile architexture to combine integer-pixel and integer cosine transform and then extend this architecture to realize the inverse integer cosine transform. These versatile architectures we design have greatly reduce the hardware cost and lead to a possibility to realize more complicated algorithm and eventually improve the performance of our encoder.