The Design Of 1.8GHz Low-Noise Wide-Band VCO

With the development of wireless communication technology, VCO, as a key component of the PLL frequency synthesizer is now widely used in RFIC.In recent years, under the trend of smaller size, higher frequency, lower power dissipation and lower cost for RFIC, the design of a kind of high performance VCO using standard CMOS processes becomes a major challenge in the RFIC.To realize a GHz wave band VCO, we can choose a ring oscillator or a LC (Inductance-Capacitance) oscillator. Due to a better phase noise performance, the task of the work is to design a kind of high performance LC VCO based on CMOS RF processes on the basis of analyzing the fundamentals of VCO.Based on the study of linear time invariant(LTI) model,nonlinear time invariant(NTI) model and linear phase time varying(LPTV) model,this paper discusses the underlying physics of LC-VCO in detal.With the noise model presented,this thesis obtains the expressions of phase noise in different frequency region.The general process of LC-VCO's design and optimization is summarized.Then,the thesis analyzes the model of on-chip spiral inductors and the realization of varactors.After that,a optimized spiral inductor model was obtained with the help of the ASITIC. The study also testifie several techniques of lowering phase noise in the SpectreRF simulator.In this work, we mainly pay attention to optimizing the performance of the VCO's phase noise and tuning rang. In this design, we use switched tuning and LC noise filtering technology besides choosing proper circuit structure and parameter of the devices to realize a better performance of phase noise and tuning rang. The circuit was simulated by Cadence Spectre RF under supply voltage of 1.8V. The frequency of the VCO ranges from 1.55GHz to 2.08GHz, and the tuning range is about 29.4%. The phase noise value is -76.2dBc at 10KHz offset from 1.8GHz carrier frequency. And the power dissipation of the circuit is only about 4mW to 6mW.