| As the chip size is shrinking,not only the number of transistors on a chip in the increasing variety of functions and also on the rise,the trend of circuit design gradually contains analog circuits and digital circuits hybrid circuit design,the complexity is greatly enhanced,verification problems are facing great difficulties. Previously the model description is only used in digital circuit , now Verilog HDL promoted a high-quality hardware language- Verilog-A HDL that can be used in circuit mixing analog and digital. Verilog-A description of analog circuits is to describe the circuit behavior,and at the same time greatly improves the SPICE simulation time,as Verilog-A accelerates the speed of simulation,analog circuit design in the early stages will be able to speed up the functional verification speed. Top-Down Design method is to identify the system architecture chips at first,and then to design,simulate,verificate layer by layer.This paper describes a LDO / Charge Pump automatic switching power management chip designed in the description language and the Top-Down flow. The first step is to determine the chip work style: four MOS that can be controlled is used to achieve the LDO mode and charge pump mode. With the chip connecting to the electricity,soft-start provides voltage to the gate of the MOS through the output clock signal provided by the oscillator,make the output gradually increased. When the output voltage reaches the requirements,the system entered the LDO mode,means that to stop providing the gate voltage by the soft start,and replaced by the error amplifier. By comparing the two input voltage of the error amplifier,the output controls the power tube,and finally the system is stable. If in certain time,the output voltage does not rise to the required value,the system entered Charge Pump model. In this mode,soft-start changes from the LDO mode bias to the Charge Pump model bias,at the same time,the four MOS break over alternately every two,in this way the output voltage can be doubled. Comparator decides the output to be high or low by comparing the output feedback voltage and the reference voltage. Low output voltage means that the output voltage does not reach the required value,the soft-start option will be chose to provide gate voltage of the MOS continuely. On the contrary high output voltage means that the output voltage has reached the required value,the error amplifier will be chose to provide the gate voltage of the MOS to make the system stable.To definite the overall construction of the chip and design the sub-module layer by layer. Firstly,the structure of the circuit characteristics and behavior characteristics of every sub-module are analysised and described by the Verilog-A,and simulated and analysised by the Spectre simulation tool of Cadence.The error amplifier is the core of the chip,its performance has a direct decision on the entire chip system performance. This paper designed a folding gate of the source of Operational Amplifiers. The advantage is that it can reach a higher gain and output voltage swing,and self-compensation at the same time,thus it is possible to reduce a pole effect on the system stability. Simulation proves that this amplifier gains a 78 dB open-loop exchanges and 62 degrees of phase margin, it can meet the design requirements. In this paper,the bandgap reference source is a basic framework,the operational amplifiers designs are in basic computing polarization. By Miller compensation,amplifier achieves the ultimate design of 72.1dB,phase margin of about 60.8 degrees.The bandgap reference source has a output voltage of 1.25V ,10-ppm/Ktemperature coefficient in room temperature about 27degrees,and power supply rejection ratio of 1.3mV / V.In addition,the paper also contains oscillators,soft-start,the election of a device and some protection device to be descripted,simulated,and validated. The soft-start module contains ten D flip-flop,through frequency division of the signal that producted by the oscillator,it has five different frequency clock signals. Then with the soft-start bias circuit,the five clock signals cause five current supply breakover at one time,it will make a rising current signal output , a dropping voltage signal output is the same explanation,it is the MOS gate voltage signal.After the Verilog-A and Top-Down design,the simulation and analysis of the LDO mode and Charge Pump have been done respectively. The results show that,whether in Charge Pump or LDO mode,the output voltage can reached about 3.74 V,a stable current of 1.11A. In the process of the voltage dropping from 5.5V to 2.7V,the system still has a stable output voltage. The chip switches automatically from the LDO mode to Charge Pump model. |
PDF Full Text Request