The Application Of RapidIO Interconnect Technology In The Next Generation Wireless Base Station

In a typical embedded system, increased microprocessor speeds are only one of the solutions to improve the system performance. High-speed cache and more advanced processor architecture continuously improve the microprocessor performance, but the research indicates that the increased speed of processor bus frequency is slower than the performance growth rate of the processor core, and the gap between the two is widening. Processor speed increase can not help to improve the interconnect performance that between processor and peripheral chip or among multiple processors in the multi-processor system. System interconnection, i.e. the speed at which various components "inside the box" communicate with each other, has become the bottleneck constraining the rate of performance of the embedded system. Although the bus performance presented an astonishing growth over the past few years, many signs indicate that the potential function of traditional hierarchical bus has been completely manifested. In order to meet the explosive demand for higher bandwidth within embedded systems and more efficient signal processing and data transmission, there is an active demand that adopting a new system interconnect technology to ensure that bus performance continues to increase and converts the processor performance to the system performance.The RapidIO architecture eliminates interconnect bottleneck by defining a high-performance, packet-switched, interconnect technology designed for passing data and control information between microprocessors, DSPs, communication and network processors, system memory, and peripheral devices within a system. The RapidIO architecture addresses the demand for higher performance by offering the bandwidth, software independence, fault tolerance, and low latency.Because of the fully consideration of RapidIO interconnect technology in respect of routing, switch, and ease of use, it will be gained far-ranging applications in the field of embedded system, wireless base station of 3G/B3G and high-performance digital signal process system.The application of serial RapidIO in next-generation wireless base station is in-depth researched in this thesis. Firstly, the RapidIO key technologies and the tendency of wireless base station development are discussed. Secondly, according to the application of RapidIO in the field of wireless communications, a design idea used serial RapidIO interconnect architecture in next-generation wireless base station is put forward. Thirdly, the feasibility and technical advantages of this design is certificated on the existing structure of base station. The FPGA design and implementation step of the certification program is exposited in detail. Lastly, the results of the software simulation and hardware implementation are presented. From the theoretical analysis and experimental results obtained, compared with other interconnection architecture, RapidIO has a significant advantage in terms of functionality, performance and cost. To the embedded systems especially the wireless base stations, Serial RapidIO interconnect technology is the best one. Up to 10Gb/s of bandwidth, low latency and low complexity of the software meet the harsh demand on the performance of rapid developing communication technologies; The technology of serial differential analog signal eliminates the restrictions on the number of pins, and resolve the backplane transmission problem. The point-to-point peer interconnection, switch interconnection and 1.25G/2.5G/3.125G three speeds available meet the needs of many different applications.