Research And Implementation Of The Adaptive Arithmetic Codec Of JPEG2000

As the new generation of still image compression standard proposed by Joint Photographic Experts Group, JPEG2000 has higher compression rate and more new functionalities than JPEG standard. As one of the important creative modules introduced in JPEG2000, adaptive arithmetic coding is more efficient than traditional Huffman coding. But adaptive arithmetic codec is also the bottle neck of the implementation of JPEG2000 due to its high complexity. So the research of adaptive arithmetic codec and its efficient VLSI implementation is important and valuable.Based on the analysis of adaptive arithmetic codec of JPEG2000 and taking account of the parallel processing of hardware, some optimizations are presented in this thesis and listed as follows:1. The optimization of the process of probability estimation. The Index table and probability estimation table are combined together and extended, which reduces the lookup table operation stages from two to one and accelerates the estimation of probability. 2. The optimization of interval update of encoding and decoding. The judgements of program branches are simplified, and parallel processing is introduced according to the characteristics of hardware implementation.3. The acceleration of renormalization. By introducing the extension of probability table and pre-detection of interval update, an one-time shifting strategy is proposed in this thesis.4. The optimization of byteout module of encoder and bytein module of decoder. Parallel processing is designed instead of serial processing, and the operation efficiency is improved greatly.In succession, we put forward the pipelined VLSI architectures of arithmetic encoder and decoder based on the optimized arithmetic. Considering of the balance between different pipeline stages, we divide the architecture of encoder into probability estimation stage, encoding interval update stage and byteout stage, and divide the architecture of decoder into probability estimation stage, decoding interval update stage and byte buffer refreshing stage. Each stage consumes two clock cycles. Then a uniform configurable VLSI architecture of codec is proposed. Good balance between speed and area is achieved by adopting configurable dynamic pipeline architecture.The proposed architectures are also implemented using Verilog HDL and synthesized in Xilinx ISE. The ISE synthesis reports show that the encoding speed can up to 67.2405M symbols per second, the decoding speed can up to 58.9135M symbols per second, and the codec speed can up to 56.977M symbols per second when they are implemented on xc2v3000FG676-6 device.