The Design And Implement Of The Reusable Inverter Quantizition And Inverter Transform Module In Video Decoder

MPEG-2, H.264 and AVS are the three popular video encoding standards and are widely used in multimedia applications. H.264 has the highest compress rate. AVS (Audio Video Standard) is established by the AVS working group of china and its compress rate is comparable with that of H.264. And MPEG-2 is widely used in HDTV and DVD applications. So it's necessary and valuable to design a video decoder chip which can support these popular encoding standards. As we know, inverter quantization and transform are the two important function modules in the video decoding algorithm. This thesis is aimed to design configurable IP modules for inverter quantization and transform which should be compatible with H.264, AVS and MPEG-2 standards and can be used IP cores in the video decoding SoC chips.This thesis introduces MPEG-2, H.264 and AVS video encoding standards in brief. Especially describes the inverter quantization and transform algorithms of these encoding standards. IDCT which is adapted by the MPEG-2 has some Fast Implement algorithms, such as Lee algorithm, Loeffler algorithms. Loeffler algorithm is adapted in this thesis to implement the IDCT. The inverter transform in the H.264 and AVS is integer cosine transform. H.264 adopts 4X4 ICT(integer cosine transform) while AVS 8X8 ICT(integer cosine transform). By Comparing among the inverter quantization and transform of these video encoding standards, suitable architectures for inverter quantization and inverter transform IP are designed and implemented.The re-configure design method is taken in account to design the architecture, namely based one architecture, Implementing the different Inverter transform or inverter quantization by configuring the re-configurable sub-module and math operation function module. Based on it, the two modules are implemented and verified. After the function verification, it is synthesized with the ISE by choosing XC4VLX100FF1513-10 chip. It turns out that the two IP can work at the 100MHz frequency or so.Low power is one significant guide line. In this thesis,some low power methods are adopted to optimize the power of the Inverter transform and Inverter quantization, for example,'0'bypass, gating clock, clock manage unit and power manage unit. After optimizing, the lower is estimated with the power compiler. The results turns out that the power of inverter transform is reduced obviously by 23% or so .