Design And Validation Of 8-bit Enhanced CPU Based On FPGA

With the rapid development of information technology, system level SoC (System on a Chip) has become the main direction of ASIC (Application Specific IC) design. SoC technology is widely used in embedded system now, for its low cost, low power, high integration and other advantages. Through studying 8-bit CPU core and implementing it on FPGA, this paper has made a try on the research and design of SoC.Based on thorough analysis of MCS-51 assemble language instruction sets, this CPU's top function and structure definition, detailed description of all modules were finished in the paper according to the Top-Down high-level design process of digital system. External interfaces, such as interrupt, serial and timer, were also added to this CPU model.8-bit CPU's data path was designed under five kinds of addressing system. The controller path is based on FSM and micro-program. Combining combined circuit with time sequence circuit, external interfaces were carried out. Because of edge triggered flip-flop, a machine period is equal to a clock period, which improves the execution efficiency. Every level unit of the design was programmed with Hardware Description Language (HDL). Every unit's module of the CPU was programmed, debugged, placed and routed in EDA environment of ISE. The CPU was synthesized by Synplify Pro. Function simulation and post placed and routed simulation were carried out by Modelsim SE.An extended interfaces controller was also designed which includes 8 high-speed DI and DO interfaces and 2 SPI interfaces.The coprocessor improves the CPU's ablility and can be used on other CPUs.The CPU model in this paper can execute all 111 instructions of MCS-51 assemble language instruction sets, and is better than the traditional MCS-51 MCU on both clock frequency and the execution efficiency of the instruction. This design was existed in a form of HDL source code, which can be reused in many SoC designs. This model can be read easily, updated easily and extended freely, so it has a practical value in SoC design. This design was implemented on FPGA.