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Design Of Digital Module Of RF Chip Used In Mobilephone Handset

Posted on:2008-01-20Degree:MasterType:Thesis
Country:ChinaCandidate:L SunFull Text:PDF
GTID:2178360242460780Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
In this thesis, the digital module of CHRF06G/GSM/E-GSM/DCS/PCS RFchip used in mobile phone handset is researched and designed. The decimating,filtering and digital down converting of the digital signal are accomplished by thedigital module of the RF chip.The module is composed of the digital decimation filter of Sigma-delta ADCconverter, the digital down converter and the frequency selecting low pass filter.The signal decimating and quantizing are competed by the digital decimation filterof Sigma-delta ADC converter. The digital signal is separated to the broad bandpart and narrow brand part. The narrow brand part is picked up. The signalsampling speed required is reduced, so that the data stream and the workload of thebase band is reduced. All the wok is competed by the digital down converter. Theunused signal is filtrated and the noise of the signal is attenuated by the frequencyselecting low pass filter.In the thesis, the theory and the criterion of the digital modules of RF chip arefirstly researched. System modeling and function simulating are carried out tovalidate the algorithm and the function of the modules. The work is accomplishedunder the Matlab programming language. Then, the spec of the design is writtenand the modules of design are divided. The RTL code and the testbench of themodules for the design are written using the verilog, and the simulating platform isbuilt for verification of the design. Lastly, the design is synthesized by the DesignComplier tool based on the standard 0.18μm CMOS process.It is illustrated from the result produced by the VCS tool that the digitalmodule of the CHRF06G/GSM/E-GSM/DCS/PCS RF chip used in mobile phonehandset can realize all the function required. The area occupied by the module inthe design is 0.03mm~2. which is given by the Design Complier tool based onstandard 0.18μm CMOS process. The design has an improvement on the precise ofthe data processing, power consumption and the area occupied.
Keywords/Search Tags:Radio Frequency, Digital Fliter, Digital Down Converter, Sampling Signal
PDF Full Text Request
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