Design And Implementation For Scheduling In LOBS Network With FPGA

Labeled Optical Burst Switching (LOBS) network, combing the Multi Protocol Label Switch (MPLS) and OBS technologies, has the advantage of high flexibility and high efficiency. Based on the project "LOBS Network Testbed" supported by the national 863 program, in this paper, the design and implementation of the channel scheduling algorithms in edge node and core node of LOBS network are studied as well as the hardware interface between FPGA and embedded processor.The background of LOBS technology, architecture of testbed and the frame structure of the edge node and core node are introduced firstly in this paper.In this paper, the design of the scheduling module with FPGA in edge node is described in detail, including module for information exchange, addressing and buffering module, frame receiving and sending module, and channel resource scheduling module, and son on. The burst information is exchanged with assembling FPGA in information exchange module. Addressing and buffering module are used to exchange messages between FPGA and embedded processor and carry on the read and write operation to different buffering area.In this paper, the FPGA design in core node of LOBS testbed is also discussed in detail. The modules in core FPGA include scheduling modules, interface module for embedded processor, interface module for optical cross matrix and addressing and buffering module, and so on. The designs of these modules are also described in detail.Finally all involved technologies are summarized in this paper and some suggestions for improving the performance of the design are also put forward.