Analytical models for chip multiprocessor memory hierarchy design and management

Continued advances in circuit integration technology has ushered in the era of chip multiprocessor (CMP) architectures as further scaling of the performance of conventional wide-issue superscalar processor architectures remains hard and costly. CMP architectures take advantage of Moore's Law by integrating more cores in a given chip area rather than a single fast yet larger core. They achieve higher performance with multithreaded workloads. However, CMP architectures pose many new memory hierarchy design and management problems that must be addressed. For example, how many cores and how much cache capacity must we integrate in a single chip to obtain the best throughput possible? Which is more effective, allocating more cache capacity or memory bandwidth to a program?;This thesis research develops simple yet powerful analytical models to study two new memory hierarchy design and resource management problems for CMPs. First, we consider the chip area allocation problem to maximize the chip throughput. Our model focuses on the trade-off between the number of cores, cache capacity, and cache management strategies. We find that different cache management schemes demand different area allocation to cores and cache to achieve their maximum performance. Second, we analyze the effect of cache capacity partitioning on the bandwidth requirement of a given program. Furthermore, our model considers how bandwidth allocation to different co-scheduled programs will affect the individual programs' performance. We find that the best chip-level performance is obtained when we carefully coordinate cache capacity partitioning and bandwidth allocation.;Since the CMP design space is large and simulating only one design point of the design space under various workloads would be extremely time-consuming, the conventional simulation-based research approach quickly becomes ineffective. We anticipate that our analytical models will provide practical tools to CMP designers and correctly guide their design efforts at an early design stage. Furthermore, our models will allow them to better understand potentially complex interactions among key design parameters.