Research On Digital IF Receiver Of Satellite Navigation System By Using FPGA Devices

This dissertation investigates the subject about PN code acquisition and tracking method of Digital IF Receiver of Satellite Navigation System under high dynamic and large frequency offset environment. The high dynamic spread spectrum signals include high Doppler shifts which may exceed 10 kHz, besides the receiver works under large frequency offset environment, which increase the difficulties of acquisition process. This dissertation presents a DMF architecture use long period PN code, partial correlation mode has been implemented to counteract Doppler shift influence. Multi-accumulated correlation value method is adopted to avoid setting determination threshold, and system detection-rates are calculated under these circumstance. A new acquisition strategy based on Two-dimensional searching is proposed to reduce the time consumption of PN code acquisition.A VLSI architecture of digital delay-locked loop is proposed in this dissertation, then the method of calculating loop filter parameter is also studied. Digital down conversion is adopted for Doppler shift compensation. A VLSI architecture of Costas loop for carrier synchronization is presented.The whole system is implemented on FPGA, at the end of this dissertation some FPGA implementations of prime modules and analysis of simulation result are presented.