High Level Modeling In The System On Chip Design

With the development of the design technique of the System-on-a-chip, the complexity of the SoC is increased. How to grasp the whole SoC before the design become more and more difficulty. In this thesis, how to rapidly and exactly build the SoC model for evaluating and optimizing the SoC before the design is researched.Firstly, in this thesis, some kind of modeling tools are compared, and because the embedded core of our designed SoC(Garfield) belong to ARM Ltd.So the ARMulator of ARM Ltd is selected for the modeling tool.Besed on the ARMulator, the external memory interface(EMI) model is builded, and is compared with the true chip. The results show the veracity the ARMulator is reached 95%.Secondly, using the model of the EMI, the optimizing the performance of the EMI of the Garfield is researched. Aim at the ARM7TDMI of the Garfield without the CACHE, using the burst transfer of the SDRAM, some caches are added in the Emirs the data or instruction can be perfected to the caches. So the access to the SDRAM is decreased and the performance of EMI is increased. The results of simulation show that the performance of the Garfield can be improved 50%.Finally, the AMBA bus model and the peripheral interface functions are bring forward. the bus model is made up of the interrupt controller(INTC), AHB and APB. The peripheral interface function is composed by the AHB interface function and the APB interface function. Using these interface functions, most of the peripheral models can be built before the design. So the whole SoC system can be built in the ARMulator before design. Base on the AMBA bus model.