The Study Of Radar Signal Process And Image Display Based On FPGA

The radar signal process is the most important component of the VTS. The yamp process must be completed on very short time, about(0.05 — 0.1us) one distance unit. The yawp process such as(CFAR) is very complex, and have to complete on very short time, Image display system must change polar coordinates into Cartesian coordinates quickly. It can be fulfilled on precision by software, but it can not be completed on time. So these tasks can be resolved by application specific process. Nowadays FPGA can resolve so many tasks on the digital signal process field, and FPGA is very important by excellent performance on the digital signal process field. The CORDIC algorithms can complete some functions with higher precision on hardware. In this paper, aimed at these points , the arithmetic of CORDIC is implemented in radar signal process. Basic functions and operations, such as sine wave, cosine, tangent, multiplication, division, exponent and logarithm, are implemented with hardware, which can be designed into repeated IP core. This design can result the problems for the real-time and precision. The algorithms can be transferred in the research of radar in the future. This mean can save vast time and reduce the difficulty in the arithmetic research. Aim at radar signal processing, this paper mainly does as follows:1. analyzing and researching the CORDIC algorithms and the infection that it brings in the radar signal processing.2. Simulating the code in the condition of ISE belonging to Xilinx , simulating by Modelsim and synthesizing by Synplify.3. analyzing the experiment results' pace and precision.4. analyzing and studying the correlation arithmetic used in the radar signal process and image display.5. analyzing the infection in the arithmetic and the IP's application in the radar signal processing from the IP core's characteristic.