Key Technologies Of Radar Signal Reconnaissance Digital Receiver Based On FPGA

As the development of signal processing and electronic technology, the system of radar signal reconnaissance receiver has been changed from analog to digital. The emergence of software radio concept prompts the development of wideband and full interception of radar reconnaissance. Present serial signal processing structure was difficult to meet the system's requirements. However, the invention of FPGA device makes it convenient to realize such a wideband radar signal reconnaissance digital receiver.According to the characteristics of FPGA chip, several novel algorithms and hardware implementation technologies of radar signal reconnaissance digital receiver have been researched, which were based on the previous research achievements of our group. The main contents and innovations of this dissertation were following.1) Two kinds of co-simulation technologies, such as Matlab/ QuartusII and ISE/ModelSim/Matlab, were presented to implement FPGA. The design efficiency of radar signal reconnaissance receiver using FPGA could be improved greatly by these co-simulation methods.2) A wideband digital In-phase/Quadrature(I/Q) transformation algorithm based on FFT/IFFT was presented. And then it was implemented in FPGA. This design can complete a real time continuous I/Q transformation of he input data with 600MHz bandwidth.3) A full parallel FFT arithmetic and its implementation in FPGA were presented. The total 32 points FFT computation could be accomplished within only one clock cycle. The operation speed can meet the requirement of the channellized digital reconnaissance receiver. 4) A self-correlation signal detection algorithm and its implementation in FPGA were presented. By modifying the FIFO depth, the length of self-correlation can be altered conveniently, which could be used to detect weak signal. The thorns and protuberances appeared while detecting radar pulse would be eliminated through setting the second threshold. The probability of false alarm is reduced and the reliability of detection result improved.5) A effective multi-channel self-correlation signal detection algorithm was proposed. The basic structure of this algorithm included three channels. Each channel was an independent self-correlation cell with different correlation length and detection threshold. Through combining the detection results of three independent channels, final detection result was given. The implementation procedure of this algorithm in FPGA was presented. The co-simulation results showed that the signal detection capability can be improved greatly.6) A fast and accurate frequency estimation method, which was derived by interpolating between two maximum FFT coefficients, was presented. Then it was implemented in FPGA chip. In order to reduce operation delay and save hardware resources, only real or image part of the two maximum FFT coefficients were used when implementing this algorithm in FPGA.7) Summarizing the results presented above, a radar signal reconnaissance digital receiver was implemented in a single FPGA chip. The capabilities of intercepting radar signal, estimating arriving time, terminative time, pulse width and pulse frequency can be obtained by this single chip receiver at real time. Finally, the receiver was tested in microwave darkroom.