Suitable For Wlan 802.11b Receiver Mixer Design

In recent years, there is much interest in research and design of low cost, low power CMOS receivers as wireless communication systems grows rapidly. With the continual advance of CMOS technology, the intrinsic frequency (f_t) becomes higher and higher. Most building blocks of radio frequency (RF) receivers can be fabricated in CMOS technology and the on-chip passive devices (on-chip inductors and capacitors) as well, which makes it possible to integrate all components of RF receivers into one chip. This work is carried out against this background, and focuses on research and design of down-conversion mixer, which is the key component of the receiver.First of all, this work briefly introduces several common architectures of RF receivers and shows the architecture adopted by WLAN 802.11b standard. Afterwards, it explains the meaning of important performance specifications of mixer block and receiver.Secondly, this work introduces the basic operating principle of mixer and several types of structures as well. Theoretical analysis of important on performance (linearity, conversion gain, noise etc.) posed by design parameters is given. The curves show intuitive relationship between mixer performance and design parameters, such as width and length of MOS transistors.Next, a high performance mixer is investigated based on the aforementioned analysis to satisfy the specification of WLAN 802.11b receivers. Optimization of transconductance pair and proper DC bias of tail current stage are key problems in the design. The mixer is based on double balanced Gilbert-cell, and implemented in SMIC 0.35um RF CMOS technology. Cadence SpectreRF Simulation results show that the mixer reaches a -5dBm IIP3, 17dB SSB NF, and 10dB gain. Performance meets design specification basically.Finally, this work draws a conclusion from the simulation results and it will play an important rule in future improvement of the mixer.