The Research And Circuit Design Of System Constructing Frame In Baseband Of DS-UWB

UWB is a new wireless communication technology in recent years. During the development of UWB,there are mainly two groups MBOA with the key techonology OFDM and DS-UWB competing for the standard.Circuit realization is possible as the theory of DS-UWB is mature. The reaserch in this paper is on ciruit design of system constructing frame in base-band of DS-UWB.This system takes a very important position in communication system. The system mainly including three modules source encode,channel encode and interleaver can be used to ensure the data correctly recovered in destination.At first, this paper introduces the frame of baseband in detail. The introduction contains the structure of the frame and what each part means.Secondly, analyzes the arithmetic of these three modules scrambler, convolution encode and interleaver detailedly.Besides, this paper compares convolution interleaver with other two interleaver ways in aspect of real time and the complexity of the circuit structure, and chooses the convolution interleaver in the end. According to the protocol IEEE 802.15.3a, this paper confirms the design scheme of system constructing frame in base-band scrambler,convolution encode with parameter (2,1,6) and convolution interleaver with parameter 7x10. The platform of system constructing frame in baseband is constructed in MATLAB in this paper, and also the platform of the system revivification the baseband frame for test. The data from 512x512 picture lenna is as the system's input data so the result can be shown directly. The data goes through the system constructing frame in baseband and the system revivification the baseband frame, and the data got in destination are as same as the source data. So the system's function design is correct.Thirdly, According to the protocol IEEE 802.15.3a and data sheet of MC270123 in XS110chip series from Freescale, this paper designs the constructing frame in baseband system and XII interface between MC270123 and MC270143.The system's circuit is described in verilog HDL, synthsised and simulated by QUARTUS II 5.0 . There are introductions about the system's and submodules' working principle in this paper. In this paper, the simulation result of each module is given. Besides, this paper has research on synchronous FIFO and asynchronous FIFO. The asynchronous FIFO with depth 16 words is validated on FPGA, at the situation of the period of writing clock 20ns and the period of reading clock 40ns. The result is given in picture in this paper.At last, this paper constructs the test system for the whole system and validates it on FPGA in series of cyclone II. The test system whose input is 4000 bits fixed data works in the clock with the period of 20ns.simultaneously ,the 4000 bits fixed data are processed by the system constructing frame in base-band in MATLAB. Comparing the output of circuit test system with the result in MATLAB shows they are same. So the system's circuit design can work correctly.