Convolution Code Blind Identification Of FPGA Implementation Technology Research

In the wireless communication system, the bind identification of channel coding has an extensive application. The blind identification of convolution code as a common channel coding plays an important role in many fields. But the existing blind identification of convolution code is generally searching good code with the help of computer, the realization of the hardware device is also very less. The main topic of this thesis is the hardware implementation of the blind identification of convolution code. In this thesis, the main contents are arranged as following:This thesis introduces the basic concepts, the chracter and the presentation of convolution code, and according to the encoding characteristics of convolution code, the thesis describes the types of the identified parameters and some basic principles, as well as gives some detail on the algorithm of several blind identification.This thesis discusses the blind identification of traditional Gaussian elimination algorithm, and optimizes the traditional algorithm based on the parallel characteristics of hardware implementation. the theories of the optimization process are detailly introduced and proved. The design of hardware module focuses on basic unit implementation and the consume of resources, and the thesis mianly introduces the hardware implementation of optimization algorithm, according to the parallel structure of the hardware. Finally it’s successful on the blind identification of the convolution code rate in the hardware device. And the time complexity of the optimization algorithm is decreased by two orders of magnitude other than the traditional algorithm in the software implementation.The thesis introduces the blind implementation of convolution code generated polynomial directly based on Walsh-Hadamard transform method, and the simulation of the algorithm is carried out. Then the thesis detailly expounds the process of the Walsh-Hadamard transform algorithm on the hardware implementation. It’s not applicable according to the analysis of the time series and resource utilization. The process is optimized by the algorithm recognition on hardware implementation and then the thesis demonstrates the correctness of the conclusion. Finally the identification of convolution code generating polynomial is successful implemented in hardware device. It can be seen that the timing performance and resource utilization are optimized a lot according to the hardware implementation of comprehensive report.