Hardware Design And Implementation Of The Key Modules Of JPEG2000 Encoder

JPEG2000 is a still image compression standard proposed by Joint Photographic Experts Group. Many new technologies are adopted by JPEG2000, such as Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optimized Truncation (EBCOT), which obtains about 50% bit rate reduction compared with original JPEG standard. As DWT and EBCOT are the key modules of the JPEG2000, the implementation efficiency of these modules will affect the performence of JPEG2000 codec directly. So it's important and valuable to research these modules of JPEG2000.In this thesis, the theories of DWT and EBCOT of JPEG2000 standard are analyzed in detail, and the frameworks for DWT and EBCOT are designed and optimized. The pipelines and timing structures are also presented. The designed structures of DWT and EBCOT are simulated and verified on FPGA platform, and the simulation results are also presented.Orthogonal wavelet basis is choosed by DWT as the transform basis. Compared to the widely used DCT, DWT has the excellent capability of compression and scalability for video coding, but also has high complexity. In order to reduce the complexity lifting scheme is selected by JPEG2000 standard to implement discrete wavelet transform. In the hardware design of DWT, this thesis proposes a lifting wavalet unit which has uniform format and clear hiberarchy. By changing the combinational logic of shifting circuit, the lifting schemes of LeGell5/3 and CDF9/7 can be realized flexibly. In this thesis, the control mechanism of 2D DWT is optimized. In the proposed mechanism, the row transform and the column transform of 2D DWT are performed alternatively, and the column transform is performed along the row direction. By introducing the buffer control mechanisim for row transform the memory requirements are reduced and the processing speed is accelerated. The DWT architecture proposed by this thesis has the advantages of high processing speed, high efficiency of hardware resources and low memory requirements.EBCOT is one of the core modules of JPEG2000 standard. The decision logic of EBCOT is very complex and the date access rate is also high, which are not appropriate to hardware implementation. So a new bit-plane coding scheme of EBCOT is designed in this thesis, which can fulfil three passes'coding by only one-time scan. So the coding speed can be improved significantly and the data access rate can also be reduced.Based on the analysis and research of relative theories the hardware circuits of DWT and EBCOT are designed using Verilog HDL and their performances are also optimized. Finally, these designs are all simulated and verified as Virtex2-xc2v1000 FPGA selected as the target platform. The experimental results show that the DWT encoder can run up to 100MHz and the EBCOT encoder can fulfil the coding of 32x32 block in limited time under 50MHz frequency. The DWT and EBCOT designed by this thesis can be used as compact and efficient IP core for JPEG2000 VLSI implementation.