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Bit-field Optimization And Function Inlining For IXP Network Processor

Posted on:2006-05-07Degree:MasterType:Thesis
Country:ChinaCandidate:W TangFull Text:PDF
GTID:2178360185496974Subject:Computer system architecture
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Network processor is a new generation of ASIP processor optimized for network processing. Optimized design allows network system to forward packets at wire speed. Software programming environment provides programmer a flexible interface, which makes it easy to implement a variety of network processing protocols and services. Such an environment reduces the development cost and time to market. However, current environment needs software engineers to be familiar with hardware architecture. This degrades portability and reusability of applications. With the increasing complexity of hardware, it will put more loads on programmer. So new program environments freeing programmer from architecture details comes into requirement. Project targets to such goal.Unconventional architecture of network processor exposes new opportunities to compiler. This thesis introduces two independent compiler optimizations: bit-field optimization and inline expansion. Both, implemented in the project, are target to IXP architecture.Bit-field optimization introduces bit information into traditional data flow analysis, constructs def-use and use-def link pair and generates efficient machine code using pattern matching. The experimental result shows that this optimization can reduce instructions by 1.1%-3.7%.Inline expansion is a classic compiler optimization. New features of IXP network processor expose new optimization opportunity. With critical path extraction and iterative compilation support, function inlining can perform inline analysis and expansion more efficiently. Test result shows that forwarding rate of the network system increases 8%.
Keywords/Search Tags:network processor, function inlining, bit-field optimization
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