Research And Implementation Of FFT Algorithm In The SAR Real-Time Processor Using Virtex-Ⅱ Pro FPGA

Based on the principle of synthetic aperture and pulse compression technology, Synthetic Aperture Radar(SAR) broke through the limitation of real antenna aperture realized 2-D high-resolution imaging to distant targets, and got widely used in both military and civil fields.Fast Fourier Transform(FFT) plays a important role in radar imaging algorithms, and float data form is usually adopted in SAR signal processing because of its big dynamic range and high precision, so how to accomplish float FFT process quickly and effectively determines the performance of the SAR real-time processor directly. To complete FFT using high-speed DSP chip is thought to be the best method in the past, but in recent years, FPGA has developed so quickly that it has a better performance in signal processing than DSP now. This thesis focuses on the implement of float FFT based on Virtex- II Pro FPGA and the SAR real-time imaging processor.Chapter 2 explains the essentials of synthetic aperture radar, analyzes the range resolution and azimuth resolution, then introduces the range-Dopper imaging algorithm in detail and presents the base architecture of real-time imaging processor based on the R-D algirithm.Chapter 3 introduces the main features and design-flow of Virtex- II pro FPGA, as well as its development environment-ISE 7.x and the emulator-ModelSim.Chapter 4 studis the radix-2, radix-4 FFT algorithms that have been used mostly for practical applications due to their simple structures, with a constant butterfly geometry and the possibility of perform them "in place", realized the float 16k point FFT based on one Virtex- II Pro FPGA chip and validated it.