Research Of Adaptive Filter Based On FPGA For EEG Signal Processing

Electroencephalograph (EEG) is a significant instrument to prevent, diagnose and treat epilepsy etc. in medicine, which is an important means for exploring human's thinking and trainning intelligence. EEG is faint in a background of strong interference, so most hospitals adopt special shielding room to detect EEG signal so that patients can't be inspected in time. At present, many hospitals adopt new digital EEG apparatus to detect out of the shielding room. But it has not been widely used, and its performance is not ideal. So it is necessary to develop an EEG apparatus which can detect EEG in strong interference background.In this paper, we analyzed the characteristics of EEG signal and discussed its interference background. A scheme is proposed for the EEG signal acquisition system. The EEG signal acquisition system is consisted of four parts, which are EEG pre-processing, digital signal processing circuit, digital signal processing software and upper machine acquisition. The main context of the paper is presented as follows:Firstly, according to the characterstics of EEG, we discussed the existing digital filter methods and compared their characters. On this base, adaptive filter is proposed and applicated in EEG processing. Secondly, analog EEG detecting system of higher CMRR is designed and gets well effect. Thirdly, we analyzed the principle of adaptive filter, whose superiority and flexibility are proved by simulation. Lastly, the hardware circuit of digital acquisition system is designed, and the programs for system controlling and adaptive filter arithmetic are designed. EEG can be observed clearly after D/A switching. At the same time, EEG data is transmitted to the upper machine by serial communication,so we can see EEG waveform by virtual instrumentation. We also analyzed frequency characteristics of different EEG.The emphases of this paper are to demonstrate the feasibility of adaptive filter and its realization in FPGA. Adaptive filter technique is used to filter 50Hz power line interference and baseline shift. The feasibility of adaptive filter is demonstrated through simulation. The parameters of the algorithm are decided by the hardware and the algorithm itself. The algorithm's FPGA realization concludes hardware circuit and programming. In hardware circuit, EPF10K30E is chosen as core unit of control and operation. According to the characteristic of this algorithm, complement code mode circuit is used in both A/D converter and D/A converter. In addition, to follow up the...