Network Processors, Packet Classification Engine Design

With the rapid development of Internet and the appearance of new technologies, it is in great need of the backbone network equipments with the high performance and programmable character. So a new kind of processor called Network Processor (NP) is emerging. It is a high-powered and programmable processor that specially deals with network business. At the same time, NP needs to classify the coming packet and satisfy some new complex network applications, such as filtering the packet, differentiated qualities of service, QoS, Multicast and so on. So packet classification is becoming a key in the design of network processor.In the program "Research and Application of High Performance Network Processor" assisted by national fund of natural science, the author is responsible for the design of packet classification engine in the network processor. The research work of this dissertation mainly includes:1. Analyzing the architecture for network processor, and making effort to find the future possible direction for NP. At the same time, summarizing the technologies of the packet classification, classifying the existing packet classification algorithms and comparing the performance for the different algorithms.2. Using the folded vector in the Tuple Space Algorithm, an improved algorithm called Tuple Folded Vector Algorithm (TFV) is presented.3. Analyzing the hardware implementation method for packet classification engine and proposing a method that constructs classifier based-on multi-field decomposed algorithm—AFBV. Designing a module for the packet classification engine in hardware according to the classifier.4. Writing the RTL (Register Transfer Level) module and verifying the functions for the packet classification engine module using VerilogHDL. At last, analyzing its performance.