Research And Implementation Of Parallel Logic Simulation System Based On VHDL

It is known that simulation plays an extremely significant role during the design of digital circuits by using VHDL attributing to its real-time feedback for the designed result, through which the existed flaws can be detected. However, with the increasing tendency of the scale and complexity of VLSI systems, the traditional sequential simulation is gradually becoming the bottleneck of the design. As a result, parallel VHDL simulation has attracted more and more attention owing to its huge potential to improve the rapidity of simulation.A parallel logic simulation system denotes a particular simulation model based on PDES (Parallel Discrete Event Simulation), through which the total simulation time can be effectively reduced attributing to the implementation of the workload of the simulation to distribute to the processors of a parallel computer or a network of workstations. As for a parallel logic simulation, the attention is focused on the effective partitioning of the circuits and its direct impact on the effectiveness and rapidity of the parallel logic simulation. Generally, it is necessary to improve the static partitioning logarithm and to employ a dynamic load balancing one when optimum effectiveness can not be achieved by the traditional adopted static partitioning logarithm. Correspondingly, the workload of each processor can be kept balance by the partitioning and dynamic adjusting of the workload according to the status of each processor during the simulation process. As a result, the simulation performance and rapidity of the circuit is updated, and therefore a highly active, stable and reliable parallel logic simulation system that is suitable for VLSI systems can be established. In this dissertation, the corresponding investigations have been carried out by employing the parallel method and logic simulation, listed as follows.(1) Presented a researching idea of parallel logic simulation implementation.