Design And Implementation Of Load Balance And Packet Forwarding In Network Processors

Network processors are the key devices to forward packets in the routers. As there is inherent parallelism in the packets processing, network processors adopt many parallel technologies to accelerate the processing of the packets. The parallel architectures of the network processors are explored in this article and the parallel technologies adopted by the network processors are divided into three aspects. They are the parallelism inside the PEs(Processing Element), the parallelism between the PEs and the parallelism between PEs and coprocessors. The distribution schemes of packet influence the performance of parallelism.As the scheme of packet distributed influence the performance of parallelism, in this paper, the HDW(Hash-based Dynamic Weight) scheme for allocation packets in network processors is presented. The scheme is building and keeping one mapping relationship between packets'identifier and PEs in a table of hash. The mapping formula is derived from the HRW( highest random weight ) scheme, it is complemented by a feedback control mechanism designed to monitor processor's utilization. A dynamic extension to the HRW scheme is provided in order to cope with biased traffic patterns. Simulation results indicate that the scheme achieves significant improvements the load balance of processor and minimizes the probability of flow reordering.On the validate platform of network processors, this paper implements the prototype of network processors chip. The prototype designs with soft-core processors of Nios II in FPGA, improves the programmability of network processors. It implements high-speed routing lookup based on TCAM and IPv4 packet forwarding function through software. We have designed and finished the software module development, including boot microcode of Nios II,packet forwarding and filtrating.