Design And Implementation Of Acquisition, Processing And Display Sub-System In Video Communication System Based On DM642

Along with the arriving of information age, the technologies of information processing, especially the video information processing, have been developed rapidly. The video communication system has been widely applied in video conference, video monitoring and other fields. When developing the video communication system, the hugest obstacle is the video acquisition, display and algorithm processing, because the video communication system need to be high-speed, steady and flexible, while handling the mass video data. Therefore, constructing the system for video acquisition, processing and display is becoming the key point of the actual application system design in WAN/LAN, and has drawn great attention.This dissertation proposes a design and implementation scheme of video acquisition, processing and display sub-system/terminal system based on DM642EVM board. Embedded technologies, multi-way technologies and sampling technologies are used to reduce the sampling rate by software, so that the system can provide appropriate image format according to the condition of network and can eliminate aliasing noise. The system also uses motion detection to control the frame rate. Therefore, the system can save transmission bandwidth effectively and design to provide multiple degrees QoS according to the network condition.The DM642EVM, which is based on the second-generation efficient and advanced VelociTI very long instruction word architecture, is developed by Texas Instruments, and using such DSPs is an excellent choice for digital media applications. The DSP core of the DM642 is 32-bit fixed-point DSPs of C64x, with the performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600MHz. The DM642 uses a two-level cache-based architecture, Level 1 cache is composed of a 16-Kbit L1P (level 1 program cache) and a 16-Kbit L1D (level 1 data cache), Level 2 cache consists of 256-Kbit memory space that is shared between program and data space. The peripheral elements include: three configurable video ports, a 10/100 Mb/s Ethernet MAC (EMAC), a management data input/output (MDIO) module, a VCXO interpolated control port (VIC), one multichannel buffered audio serial port (McASP0), an inter-integrated circuit (I2C) Bus module, two mulitchannal buffered serial ports...