Memory Fetch Module Design In H.264 And AVS High-Definition Video Decoder

This thesis makes an analysis and research for the module of reference data memory fetch in high-definition video decoder chip, which supports both H.264 and AVS standard, and gives a feasible hardware architecture for the module. The memory fetch module belongs to the part of motion compensation in video decoding, and the module function is computing the coordinate, the size and the SDRAM addresses of the integer reference block, which is used to get the predicted block of sub-pixel sample position, and then fetching all the reference data from SDRAM.The design is based on varied block size, and the memory fetching units are blocks of different size. According to a store method of reference pictures, the design implements a fast memory fetching process. This module has a strong impact on the speed of the whole chip, since it reads the memory frequently and the quantity of the fetching data is enormous. So the times of reading memory, as well as the number of clock cycles, has been saved as few as possible for the requirement of real-time decoding. In addition, common hardware for implementing H.264 and AVS in the module has been considered farthest, because the chip supports both H.264 and AVS standard.The arithmetic of reference data memory fetching is analyzed and researched firstly in this thesis, according to the video compression theory and the design requirement of the whole system, and then an efficient hardware architecture is put forward. The C model and RTL design have been simulated and debugged, and the RTL code design has been synthesized. Ultimately the timing and area requirements of the chip design are both satisfied.