Research On The Memory Management Of Digital Video Decoders

Bandwidth requirement and energy consumption of memory accesses are always the bottlenecks of the system performance in high-speed mass data processing systems. Cost-constrained high definition video decoding system is a typical one that is bothered by the frequent and random memory accesses. Efficient schemes of embedded compression (EC) and memory access management are proposed and implemented to resolve the problem of memory bottleneck for video decoding systems.Embedded compression is an attractive strategy to reduce the amount of memory accesses between the processing core and external memory in video decoder. A lossless and low-cost dictionary-based EC algorithm is proposed for high definition MPEG-2 video decoder. About 50% of data storage can be reduced with the EC schemes, which is approximate to the previous lossy schemes. Synthesized with HJTC 0.18μm CMOS technology, the number of occupied logic gates for EC encoder and EC decoder are 13K and 4K respectively, less than 5% of that of the video decoder. Moreover, an efficienct 5/3-DWT based EC algorithm is proposed for H.264 decoder, and 70% of memory accesses can be reduced. This EC algorithm is more efficient than the existing schemes while maintaining comparable video quality. In this algorithm, each 4×4 pixel array is compressed into 64-bit or 32-bit segments to heighten the data bus utilization.Reference pixel fetching mechanism in motion compensation is the key point for the integration of EC schemes in video decoder. Boundary judgment and dual-mode boundary joint schemes are proposed for MPEG-2 and H.264 decoder respectively to provide seamless integration for the block-based EC approaches. And the new concept of EC and motion compensation combination design is proposed. In addition, the dual-mode boundary joint scheme can reduce the rate of fetched redundancy pixels involved in EC schemes to only about 10%. In the aspect of memory access management, an efficient window-based frame storage architecture is proposed, and about 90% of the lantency of page breaks (row activation and precharge) can be reduced compared to the traditional linear storage architecture. Moreover, multi-port SDRAM controller is used in the VLSI video decoder to perform the frequent memory accesses. Group-access-based response and no redundancy accessing schemes are adopted in the dedicated memory controller to reduce the number of row-activation operations, and 75% of buffer size is also saved compared to the previous works.Finally, the proposed lossless EC algorithm and boundary judgment reference pixel fetching scheme are integrated into an MB-level three-stage-pipelined MPEG-2 video decoder. The whole video decoder with EC engine is verified and tested based on Xilinx Spartan-3 FPGA platform, and can reduce 25% of power dissipation when decoding the bit streams of CIF format. It is confirmed that the proposed schemes are efficient for resolving the high memory bandwidth and high power consumption problems in the cost-constrained high-speed data transfer systems.