Simulation And Synthesis Validation Of AES Algorithm IP Core

AES is a new data encryption standard which bring forward by NIST in Oct 2000. It has substituted the Data Encryption Standard (DES) which has twenty-year application history. The paper studies the application of AES IP Core, based on the algorithm of AES (Advanced Encryption Standard). We designed the software and hardware IP based on a new way which is both from top to bottom and from logic level to physics level. We have to insure the correctness of each level in order to ensure the correctness of top level. At the beginning we design the architecture of AES, then codes, simulate and validate the algorithm. There are four levels on the simulation and validation. The first level is coding and simulation of language C. The second level is coding, simulation and validation of language SystemC. The third level is coding, simulation and validation of language Verilog. The last level is cooperate-simulation and cooperate- validation of SystemC and Verilog. Finally, AES algorithm validates on archetype, which codes on RTL level by Verilog language, simulates, validates and runs on FPGA. The test result accords with our requirement. The paper also studies a new language in our design——SystemC. Research of SystemC is very hot at abroad, but there is a little research in our country. Through the project of AES IP Core designing, we investigate that how many merits of SystemC language bring into the traditional IC design flow. And give an impersonality standpoint about SystemC language.