Research Of Color Image Compression System Based On PDVQ

In order to realize images' real-time compression and transfer, research team invented a real-time image compression chip which based on PDVQ algorithm. The chip can real-time accomplish the compression for gray images. However, the real world presentation format that gives people is colorful scene. Only color images can truly reflect the objective world. Color information is a very important visual feature of color image, so the compression of simple gray images is restricted greatly in actual application. Therefore studying and developing the color image compresses system is extremely urgent.On this basis, this paper proposed a project of color image compression based on PDVQ. Based on the gray image compression PDVQ chip, this paper established the outer-ring circuit on FPGA, linked the outside camera and PDVQ image compression chip, and transmitted the compression data to PC machine. Receive compression data with VC6.0 and decode image, then show the image. Finally, complete a color image compression system based on PDVQ.At the same time, as gray image codebook can not compress the color images very well, this paper proposed a color image vector quantization codebook design plan. Several codebooks which are suitable for the color images coding were designed out using classical LBG codebook generating method. Using these codebooks, several standard color testing pictures were coded, and their functions were compared. Ultimately, high performance and suitable dimension's color image vector quantization codebook were confirmed. Compared with the gradation image codebook in PDVQ chip, this color image codebook dimension is only 1/16, and the peak signal noise ratio (PSNR) value of decipher image has improved 73.51% averagely, then the matching speed also has lifted 16 times.Besides, this paper proposed and discussed an algorithm of vector quantization based on integral projection. Compared with standard VQ algorithm, the codebook stored area of this algorithm reduces 50%, and the result of experiment shows that the encode speed can be improved almost one times while the ordinary peak signal noise ratio (PSNR) only reduced 0.25 dB averagely. The feasibility of this algorithm is verified, and the algorithm is written in Verilog HDL. The coding is verified by simulation. Finally, this design is implemented in FPGA. At the same time, it is proved that the color image compression based on this algorithm has good effect.