The Influence Of Hardware Architecture On NOC's Performance And Research Of Optimization

With the rapid development of IC design technology and manufacture process, the number of transistors integrated on a single chip is increasing explosively, which results in the growing difficulty for IC design. Traditional SOC technology has met many challenges: the communication becomes the bottleneck; the capacity for reusing IP cores is limited; difficulty for the physical design increases; design for test restricted the system; and the implementation of synchronicities becomes a challenge, etc. To tackle these problems, the novel idea of network on chip (NOC) is proposed as a new solution.Firstly, this paper discusses about the design and analysis of NOC system, focusing on the design of network architecture and communication principle, which are the two key technologies in the NOC system design.Then,different design methods, including topology, buffer size, traffic distribution are proposed and compared, by the characteristics of throughout, power consumption, delay, in a platform developed by System C. Also, the paper discusses two methods to design the same amount of IP resources and it comes out with the better way to achieve this aim.At last, to solve the problem of"hot spots"generated by the traditional design in mesh topology, a modified hardware architecture is proposed with the matched routing methods, achieving better performance in both average delay and throughput.