Research On High Performance Architecture Evaluation Technologies By Simulation

Computer system performance evaluation is an important and fundamental technology in high-performance computing field, and its development accompanies that of the high-performance computing technology. Performance simulation is one of the most important tools for state-of-the-art computer system performance evaluation, and has been widely used in every stage of computer system development. It can effectively reduce the cost of computer system development and shorten its development cycle. At present, both the evaluation of new system architecture based on simulation technology and the research on high-performance architecture simulation technology itself, are becoming the hotspots in high-performance computer field.Aiming at achieving accurate and efficient performance evaluation, this thesis researches the simulation technology for high-computing architecture. The main work includes:First, the memory access performances of several scientific computing applications are evaluated on Imagine stream processor based on simulation technology. Firstly, evaluation on a typical application demonstrates that memory access efficiency is the main factor that affects the performance of Imagine stream processor; secondly, we select several typical scientific programs with various computation to memory operation ratio to test their memory access efficiency, and compare them with those on general X86 processors. The results show that Imagine can effectively reduce data traffic between LRF and SRF, but can not effectively reduce the number of off-chip memory accesses. Among the tested programs, memory access efficiency of its main memory is still unsatisfying. The evaluation results will direct the performance optimization of steam processor.Second, accurate execution time prediction of sequential execution block is the foundation to achieve accurate prediction of time in parallel simulators. Current parallel simulators predict it by using the product of wall time and performance scale factor between the host and target machine. The proportion of performance scale factor is difficult to reflect the relationship of actual execution time of program running between host and target machine, which incurs a considerable prediction error. Therefore, the thesis utilizes hardware performance counters to count major performance events, and establishes the mapping model for performance events to predict the execution time of sequential execution block on target machine. The results show that this method effectively improves the prediction accuracy.Third, parallel simulators are implemented by PDES in general, and synchronization algorithms are the main factors that affect their performance. Under the circumstance of limited host memory, current adaptive synchronization algorithms usually require frequent cancel-back operations and result in descending performance. Regarding this issue, this thesis optimizes adaptive synchronization algorithm based on the out-of-core technology, which reduces the cancel-back operations caused by memory limitation by caching the unconfirmed events in disk, and improves the performance of parallel simulators.