The Pose Measurement For Space Non-cooperative Target Based On Stereo Vision

The research of new autonomous spacecraft has become the main concern of aerospace at present. The pose measurement of the space target is an important part of new autonomous spacecraft. Some key aspects of the pose measurement using binocular srereo vision are studied in this thesis, mainly including the effects of the factors on measurement accuracy, stereo matching algorithm, and their high speed parallel implementation based on FPGA to improve the speed performance of the system.Firstly, the effects of the structural parameters of binocular vision on the pose measurement of the space target are studied. Some beneficial conclusions have been drawn and they are valuable for structure installation of binocular vision in this system.Secondly, as the most important part of the pose measurement, image stereo matching including region matching and feature matching are studied in this thesis. The region matching with the normalized cross-correlation is studied and the simulation with a simple example is given. For feature matching, because the accuracy of the feature point has significant influence on the measurement precision of the pose of the space target, Harris corner extractor and SIFT algorithm are studied in this research. To stably extract features, feature matching using polar geometry constraint and RANSAC robust estimator are studied in the unknown polar geometry constraint occasions.Thirdly, to improve the speed performance of the pose measurement system, normalized cross-correlation (NCC) is implemented in this research using FPGA. Two parallel implementation architectures for the NCC are proposed. In these architectures, several novel efficient approaches are proposed to reduce logic resource usage and computation time. In general, the first N maximum value after sorting result of the NCC is useful for us during the follow-up processing. To make full usage of the FPGA resources, a novel architecture of the sorting algorithm is proposed in this research. When the FPGA chip used has low available logic resource for sorting, the architecture is further extended with RAM as indicators for sorted data to sort large data set.At last, function and timing simulation with the chip EP2S90 and develop software, and practical experiments in the specified system hardware platform, have shown that these architectures can effectively improve the speed performance of the pose measurement system.