Low-resource VLSI Architecture Design For Binocular Stereo Matching

Binocular stereo matching technology is a very important part of stereo vision system.Its purpose is to analyze the different angle images captured from the same scene,and find the positional deviation of the matching points in the image pairs,that is,the disparity,then the depth of the object can be obtained by using the principle of triangulation.Semi-global stereo matching algorithms are often used to generate real-time,high-quality disparity maps in stereo vision systems.Considering the problem of resource constraint in hardware implementation,this thesis proposes a VLSI architecture based on semi-global stereo matching algorithm to reduce hardware resource consumption and completed FPGA verification for the proposed architecture.The main contributions are as follows:(1)A pipeline VLSI architecture based on the semi-global stereo matching algorithm with low resource,high precision and real-time requirements is proposed.In order to reduce the hardware resource consumption,a higher clock frequency is used in the stereo matching calculation module,and the number of period for each pixel is increased,so that the time division multiplexing strategy can be applied to reduce the logic resource consumption.At the same time,in order to meet the real-time requirements of the whole system,this paper adopts disparity parallelism and parallel calculation of four path costs to improve throughput.(2)In the cost calculation and aggregation stage of semi-global stereo matching,this paper comprehensively considers the loss of matching precision and the consumption of hardware resources.Finally,four optimal paths are selected for cost aggregation,which can achieve good matching accuracy with low hardware resources.And in the hardware implementation of the cost calculation module,one path cost calculation module is shared for every two path directions to further reduce hardware resource consumption.(3)In order to further reduce hardware resource consumption and improve throughput,the image resolution is downsampled during stereo matching calculation,in which the number of image lines is downsampled from 960 lines to 480 lines.At the same time,in order to make more reasonable use of the BRAM resources of the FPGA,the number of image columns is downsampled from 1280 columns to 1024 columns.The downsampled resolution finally need to be restored to the original image resolution when the disparity map are output.In the range of disparity search,the disparity search range in this paper is 0?75.In order to save hardware resources as much as possible,some large disparities don't participate in cost calculation,So the actual total calculated number of disparity is 50.The entire architecture in this thesis is verified on the Xilinx ZC7020 FPGA.Through verification,the current stereo matching VLSI design can be practically applied to an binocular stereo vision system ADAS(Advanced Car Driving Assistance System).The stereo matching VLSI architecture of this paper can achieve a maximum operating frequency of 108MHz on ZC7020,and the maximum disparity is 75.The consumption of hardware resource is 19603 LUTs and 61.5 BARM(each with a size of 36 KB),and the system throughput is 31 fps(frames per second)@1280*960,which satisfies the hardware resource constraints and real-time output dense disparity map requirements of the entire system.